Switch mode power supplies or switching regulators, also referred to as DC-to-DC converters, are often used to convert an input supply voltage to a desired output voltage. A switching regulator provides power supply function through low loss components such as capacitors, inductors, and transformers, and power switches that are turned on and off to transfer energy from the input to the output in discrete packets. A feedback control circuit is used to regulate the energy transfer to maintain a constant output voltage within the desired load limits of the circuit.
A switching regulator can be configured to step up the input voltage or step down the input voltage or both. Specifically, a buck switching regulator, also called a “buck converter,” steps down the input voltage while a boost switching regulator, also called a “boost converter,” steps up the input voltage. A buck-boost switching regulator, or “buck-boost converter,” provides both step-up and step-down functions.
The operation of the switching regulator is well known and is generalized as follows. A power switch is turned on to apply energy to an inductor to allow the current through the inductor to build up. When the power switch is turned off, the voltage across the inductor reverses and energy is transferred to an output capacitor and the load. A relatively constant output voltage is maintained by the output capacitor.
Increasingly, power supply systems for mobile applications are being designed using switching regulators having both PFM (Pulse Frequency Modulation) and PWM (Pulse Width Modulation) modes of operation so as to satisfy requirements for high efficiency over light and heavy load conditions. In general, PWM mode of operation is preferred for providing maximum efficiency at heavy load conditions while PFM mode of operation is preferred for providing maximum efficiency at light load conditions. A problem faced by these types of power supply system is how to handle the transitions between PFM mode to PWM mode and vice versa in a clean and efficient manner.
FIG. 1 is a schematic diagram of a conventional boost switching regulator configured with PFM and PWM feedback control. Referring to FIG. 1, a boost regulator 10 includes a switch control logic circuit 24 coupled to drive a first power switch M1 and a second power switch M2. In most cases, switch control logic circuit 24 is a non-overlapping gate drive generation circuit and generates control signals NGATE and PGATE that are non-overlapping. The boost regulator 10 further includes an inductor L1 and an output capacitor COUT. The boost regulator 10 receives an input voltage VIN on a node 12 and provides an output voltage VOUT having a substantially constant magnitude on a node 16 for driving a load 35. The output voltage VOUT is fed back to a feedback node 18 of the boost regulator 10 to form a feedback control loop to realize regulation and control of the output voltage. The output voltage may be fed back to the feedback node directly or through a resistor divider. In the present illustration, a resistor divider circuit including resistors R1 and R2 divides down the output voltage VOUT to provide a feedback voltage VFB (on node 18) to the feedback control loop.
The feedback control loop of boost regulator 10 includes a PFM control loop 40 and a PWM control loop 44. The PFM control loop 40 compares the feedback voltage VFB to a first reference voltage VREF1 and generates PFM drive signals 42 including a PFM_NDRV signal for the NMOS power switch M1 and a PFM_PDRV signal for the PMOS power switch M2. The PWM control loop 44 compares the feedback voltage VFB to a second reference voltage VREF2 and generates PWM drive signals 46 including a PWM_NDRV signal for switch M1 and a PWM_PDRV signal for switch M2. A mode selection circuit 48 selects either the PFM or PWM mode of operation and provides the selected drive signals to the switch control logic circuit 24. That is, the mode selection circuit 48 selects either the pair of PFM drive signals 42 or the pair of PWM drive signals 46. The selected drive signals NDRV and PDRV are provided to the switch control logic circuit 24. The switch control logic circuit 24 generates the control signals NGATE (node 28) and PGATE (node 32) for driving the first power switch M1 and the second power switch M2. The NGATE and PGATE signals may be buffered by buffers 26 and 30 respectively.
The control signals NGATE and PGATE are operative to turn power switch M1 and M2 on and off alternately so that a switching voltage VSW is generated at the switching node 14. In particular, when the switch control logic circuit 24 drives the power switch M1 to turn on and drives the power switch M2 to turn off, inductor L1 has the input voltage VIN impressed upon it, and the current through the inductor builds up. When the switch control logic circuit 24 drives the power switch M1 to turn off and drives the power switch M2 to turn on, the voltage across the inductor L1 reverses (“fly back”) and inductor L1 delivers energy through switch M2 to the output capacitor COUT and the load 35. The output capacitor COUT filters the ramping inductor current to generate a substantially constant output voltage VOUT at the output node 16.
For the PFM feedback control loop to operate correctly and reliably, a certain amount of voltage ripple is required by the feedback control loop. More specifically, because of the switching action at the power switches, all switch-mode regulators generate an output current ripple through the switched inductor L1. This current ripple manifests itself as an output voltage ripple principally due to the equivalent series resistance (ESR) in the output capacitor COUT placed in parallel with the load. The ESR of the output capacitor COUT is denoted as a resistor RESR in FIG. 1. Recently, low ESR capacitors are preferred to realize improved efficiency and low output voltage ripple in switching regulators. However, the low ESR capacitors do not generate sufficient output voltage ripple for meaningful feedback control. The desire for low output voltage ripple at the output voltage contradicts with the PFM feedback control loop requirement of a certain amount of ripple for reliable operation. The low output ripple signal (typically less than 1 mV) is often too small to be meaningfully used by the PFM feedback control loop of the switching regulator. Ripple injection circuits to introduce a ripple signal in the feedback loop have been described for buck switching regulators. For example, U.S. Pat. Nos. 7,482,791 and 7,482,793 illustrate examples of ripple injection circuits that can be applied in buck regulators using fixed on-time control.
Boost regulators using both PFM and PWM operation modes employ certain control schemes to control the transitions between PFM and PWM modes and vice versa. In most cases, the output voltage VOUT is used to determine the transition point. However, when the switching regulator employs ripple injection, the feedback voltage is no longer a linear divided down representation of the output voltage and thus does not provide a reliable measure of when the power supply system needs to exit PFM mode and enter into PWM mode to sustain higher loads.